SMAesH is a hardware implementation of the AES block cipher that uses masking as a countermeasure against side-channel attacks. More precisely, we use the Hardware Private Circuits (HPC) masking scheme, which provides state-of-the-art guarantees in terms of resistance against physical defaults (i.e., glitches and transitions) and composability.
The SMAesH implementation package is a generic HDL code (Verilog) that describes a hardware implementation of the AES protected with arbitrary number of shares.
Scientific publications introduce HPC and its application to the AES.
Current status:
- AES 128-bit encryption implemented
- FPGA-validated
- Lifetime stage: Public evaluation
- An Evaluation challenge with a side-channel dataset was organized for CHES2023.
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